The invention relates to the field of analog-to-digital converters (ADC), and in particular to reconfigurable delta-sigma modulator ADCs using noise coupling.
Wireless communication receivers today must support many different communication standards such as GSM, EDGE, TD-SCDMA, WCDMA, HSPA+, and LTE. This allows the wireless device to adapt to the available network resources and provide the user with the best level of service possible. This is achieved within the wireless handset hardware through the allocation of dedicated circuits for each standard or through reconfigurations of common circuits to the different standards.
One important component of the wireless receiver is the analog-to-digital converter (ADC). The function of the ADC is to digitize the received signal so it may be processed by the digital signal processing hardware or software components. The bandwidth of the input signal to the ADC will change along with the standard that is being supported. For example, 100 kHz bandwidth is required for the GSM standard, while 10 MHz is needed for LTE.
While it is possible to have dedicated ADCs for each standard this is not optimal since the integrated circuit area will increase and with it the cost. It is also possible to design an ADC for the largest input signal bandwidth and use it for smaller signal bandwidths, but this is again not optimal since the power consumption will be far from optimal for the narrow bandwidth cases and this will result in a short battery life. It is therefore desirable for the ADC to not only be reconfigurable, but also to have its power consumption scale in proportion to the bandwidth.
Of particular interest in the design of wireless receivers are delta-sigma ADC architectures. Here, numerous approaches have been use to allow for the reconfiguration of the ADC.
It is possible to change the order or the loop filter configurations. When cascaded or mash delta-sigma architectures are used, it is possible to disable blocks in the cascade, to reduce order for the lower bandwidth cases and thereby save power. For these techniques, it is not possible to achieve a reduction in power which is proportional to the bandwidth. This is because the reconfiguration involves removing components from the ADC back-end which generally are not the dominant contributors to the power consumption budget.
Another reconfiguration strategy involves modifying the clock frequency and the bias current used by the ADC components. This strategy does allow for the power consumption to scale with the signal bandwidth. It is worth noting that this requires great care to insure that the transistor and the circuit components they build remain within acceptable operating ranges. The use of PLL-based bias current generators has been proposed but this requires additional circuitry. Another point of care when changing the clock frequency is the requirements for anti-aliasing, especially when using discrete time implementations of the ADC.
The present invention offers a solution to the reconfiguration problem where the power consumption scales with the input signal bandwidth. This solution is based on the use of noise coupled delta-sigma ADCs.